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Phase 1: Create a blif format netlist by Quartus II This is a two phases task, the first phase is to create a blif format netlist by Quartus II, then the next phase is to convert this netlist to AIG (And Inverter Graphs) netlist (in form of verilog) by using ABC tool. In order to do that, you need pure gate level netlist(s) for the module(s) you care about (in our case, these modules are branch, decoder, alu and shifter.). Part 2: Introduce fault(s) in the netlist you get from "Part 1".įirst you will introduce faults in simple gates.Part 1: Generate the gate level netlist for the module(s) you are interested in introducing hardware faults in.There are several steps need to follow to finally successfully generate your own faulty instruction list for a specific program. Please be noted, for clarity purpose, not all the interconnections are shown in these demonstration schematics on this page. Then this instruction is stored in a list and will be extracted when the overall program is finished. When the simulation starts, by comparing the outputs of Decode stages (or Execute stages, depends on where the hardware faults locate), if the outputs in two MIPSs are different, we detect an affected instruction. One has no fault in it while the other has customized hardware level faults in it.įor both MIPSs, we apply the same clock and program. Faulty MIPS Test Structure SchematicĪs shown in Figure 1, we build in two MIPSs for this test. Please contact us through dan.wang at uwaterloo dot ca.įigure 1. The contents of faulty instruction list would vary from different programs.īefore you start, the "Fault Injection and Test for MIPS" package is available upon email request. If there is nothing wrong with the MIPS hardware, your faulty instruction list will be an empty list. In the end, for a specific piece of program, you will create a faulty instruction list consists of faulty assembly instruction types as the result of existence of hardware level faults in MIPS. This research is to mimic the influence that MIPS can get with hardware level fault(s) existence.
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Welcome to "Fault Injection and Test Flow for MIPS" webpage! From here you will get information of how to start your own fault test for MIPS.įirst, let's learn a bit of the background. Fault Injection and Test Flow for MIPS Go To Top